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ENGR 2705 Lab #3

Title:

Quartus II Software

Objectives:
  • Become familiar with the Altera Quartus II CAD system
  • Enter a design using schematic capture
  • Enter a design using Verilog
Preparation:
  1. Read Section B.1 of Appendix B from the previous edition of the textbook.
  2. Look over the rest of that Appendix B. We will work through it during lab.
Parts:

PC running Altera Quartus II Software

Procedure:
  1. Project Setup. Work through Section B.2 to create a new project. Set the directory (folder) to be Lab03 on the computer desktop. (Note: Move this project folder to your own removable storage at the end of the lab.) Set the name of the project to indicate it will be done with schematic capture. Record the project name in your lab book.
  2. Schematic Capture. Work through Sections B.3.1 using the directory created in step 1. Print the completed schematic and paste it in your lab book.
  3. Synthesis. Work through Section B.3.2 to synthesize your project. Correct any problems found by the compiler. Indicate in your lab book what problems if any were found by the compiler.
  4. Functional Simulation. Work through Section B.3.3 to simulate your circuit. Print the functional simulation results and paste it in your lab book.
  5. Verilog Design. Work through section B.4 - "Design Entry Using Verilog" performing similar tasks to steps 1-4, replacing schematic capture with Verilog and place similar information in your lab book.
Conclusions:
  1. Discuss how well the objectives were met.
  2. Discuss what you learned.