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ENGR 2705 - Lab #10

Title:

Latches and Flip-flops

Objectives:
  • Understand how a latch works
  • Understand how a flip-flop works
  • Demonstrate different types of latches and flip-flops
Parts:
  • PC running Quartus II
  • Altera DE2 Board
Procedure:

Part 1: S-R Latch 

  1. Specification. Create an S-R Latch with traditional inputs and outputs.
  2. Inputs and Outputs. Draw a block diagram of the circuit showing the inputs and outputs for the circuit.
  3. Truth-tables. Show the truth table for the S-R Latch.
  4. Verilog code. Using the New Project Wizard, specify (create) the working directory for this lab (you could name the directory lab10) and name this project srLatch (or something similar).  Create a Verilog HDL File and write the Verilog code that describes either the structure of a basic S-R Latch or its behavior.
  5. Functional Simulation. Perform a functional simulation of the circuit verifying it implements the truth table.
  6. Implement. Compile the circuit for the Cyclone II FPGA on the DE2 Board. Make appropriate pin assignments so that the input comes from the Toggle Switches and output goes to the user-controllable LEDs.
  7. Timing Simulation. Perform a timing simulation of the circuit using the same input combinations used in the functional simulation. Note the propogation delay.

Part 2: Gated S-R Latch 

  1. Specification. Create a Gated S-R Latch with traditional inputs and outputs.
  2. Inputs and Outputs. Draw a block diagram of the circuit showing the inputs and outputs for the circuit.
  3. Truth-tables. Show the truth table for the Gated S-R Latch.
  4. Verilog code. Using the New Project Wizard, specify (create) the working directory for this lab to be the same as above and name this project gatedSRLatch (or something similar).Create a Verilog HDL File and write the Verilog code that describes a Gated S-R Latch based on and using the S-R Latch from Part 1 as a component.
  5. Functional Simulation. Perform a functional simulation of the circuit verifying it implements the truth table.
  6. Implement. Compile the circuit for the Cyclone II FPGA on the DE2 Board. Make appropriate pin assignments so that the input comes from the Toggle Switches and output goes to the user-controllable LEDs.
  7. Timing Simulation. Perform a timing simulation of the circuit using the same input combinations used in the functional simulation. Note the propogation delay.

Part 3: Gated D Latch 

  1. Specification. Create a Gated D Latch with traditional inputs and outputs.
  2. Inputs and Outputs. Draw a block diagram of the circuit showing the inputs and outputs for the circuit.
  3. Truth-tables. Show the truth table for the Gated D Latch.
  4. Verilog code. Using the New Project Wizard, specify (create) the working directory for this lab to be the same as above and name this project gatedDLatch (or something similar).Create a Verilog HDL File and write the Verilog code that describes a Gated D Latch based on and using the Gated S-R Latch from Part 2 as a component.
  5. Functional Simulation. Perform a functional simulation of the circuit verifying it implements the truth table.
  6. Implement. Compile the circuit for the Cyclone II FPGA on the DE2 Board. Make appropriate pin assignments so that the input comes from the Toggle Switches and output goes to the user-controllable LEDs.
  7. Timing Simulation. Perform a timing simulation of the circuit using the same input combinations used in the functional simulation. Note the propogation delay.

Part 4: Master-slave D Flip-flop 

  1. Specification. Create a positive-edge triggered Master-Slave D Flip-Flop with traditional inputs and outputs.
  2. Inputs and Outputs. Draw a block diagram of the circuit showing the inputs and outputs for the circuit.
  3. Verilog code. Using the New Project Wizard, specify (create) the working directory for this lab to be the same as above and name this project dFlipFlop (or something similar).Create a Verilog HDL File and write the Verilog code that describes a positive-edge triggered Master-Slave D Flip-Flop based on and using the Gated D Latch from Part 3 as a component.
  4. Functional Simulation. Perform a functional simulation of the circuit verifying it works correctly.
  5. Implement. Compile the circuit for the Cyclone II FPGA on the DE2 Board. Make appropriate pin assignments so that the input comes from the Toggle Switches and output goes to the user-controllable LEDs.
  6. Timing Simulation. Perform a timing simulation of the circuit using the same input combinations used in the functional simulation. Note the propogation delay.

Part 5: Download 

  1. Download the S-R Latch circuit into the Cyclone II FPGA on the DE2 Board.
  2. Test the circuit.
  3. Download the Gated S-R Latch circuit onto the DE2 Board.
  4. Test the circuit.
  5. Download the Gated D Latch circuit onto the DE2 Board.
  6. Test the circuit.
  7. Download the Master-Slave D Flip-Flop circuit onto the DE2 Board.
  8. Test the circuit.

 

Conclusions:
  1. Discuss how well the objectives were met.
  2. Discuss what you learned.