Design and implement a more complex logic circuit using Altera's Quartus II software.
Download a circuit into the Cyclone II FPGA device on the Altera DE2 Board that utilizes
a seven-segment display.
Parts:
PC running Quartus II
Altera DE2 Board
Procedure:
Specification. Design a circuit that inputs a four-bit unsigned binary number and
outputs the value of the binary number to a seven segment display as a hexadecimal
digit. The hexadecimal digits are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, b, C, d, E, & F.
The case of the letters used is critical in order to distinguish each of the hexadecimal
digits. For example, 8 and B would appear the same if B were used. The inputs should
use positive logic and the outputs should use negative logic (changes 1's to 0's and
0's to 1's in outputs). Standard naming convention for the 4-bit input would be x3,
x2, x1, x0, where x3 is the most significant bit.
Define Inputs and Outputs. Draw a block diagram of the circuit showing the inputs
and outputs for the circuit.
Create truth-tables. Generate a truth-table that shows all outputs for the sixteen
input combinations. Remember the segments of the display turn on when a low voltage is
applied, so plot 0's when you want a segment to be on.
Derived simplified logic expressions. Derive a minimal SOP expression for each output.
Create Verilog code. Use the Quartus II text editor, write Verilog code that implements
the minimal SOP expressions. Paste a copy of your valid code in your lab book.
Functional Simulation. Perform a functional simulation of your circuit. Paste the
results in your lab book.
Implement. Compile the circuit for the Cyclone II FPGA on the DE2 Board. Make appropriate
pin assignments so that input comes from the switches 3-0 of the toggle switches and
output goes to digit 0 of the seven-segment displays. Record the pin assignments in
your lab book. Also, paste the FITTER SUMMARY from the report file in your lab book.
Timing Simulation. Perform a timing simulation of your implemented circuit. Paste
the results in your lab book including the worst-case propogation delay.
Download Circuit. Download the circuit into the Cyclone II FPGA on the DE2 board.
Test. Test the circuit. Record your results in you lab book.
