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ENGR 2705 - Lab #13

Title:

Finite State Machine

Objectives:
  • Become familiar with the design steps of synchronous sequential circuits
  • Design and implement a synchronous sequential circuit (Finite State Machine)
Parts:
  • PC running Quartus II
  • Altera DE2 Board
Procedure:

Design, implement, and simulate a Moore-type finite state machine (FSM) that detects when a input sequence of 110 has occured. Include as part of the design a state diagram, state table, state assignments with a state transition table, K-maps, and schematic. Perform both a functional simulation and a timing simulation.  Include the typical information in your laboratory notebook.  Download and test the machine.

Conclusions;
  1. Discuss how well the objectives were met.
  2. Discuss what you learned.